Digital Logic Theory & Design

PART – A

Date: 17-11-2006 Unit I

  1. Convert (673.124)8 into binary numbers.( Nov 2006)
  2. State deMorgan’s law. ( Nov 2006)
  3. Given the logic expression f = ABC + BC’D + ĀBC, make a truth table.( Apr 2007)
  4. State the Boolean theorems. ( Apr 2007)
  5. Convert 1110011 into hexadecimal through octal. ( Nov 2007)
  6. Simplify A + AB + A’ + B ( Nov 2007)
  7. Convert (110101)2 to Octal number. ( Nov 2007)
  8. Prove De Morgan’s theorem. ( Nov 2007)
  9. Express the following decimal numbers in 2421 and 5421 code (i) 1993 (Apr 2008)
  10. State Demorgan’s theorem. (Apr 2008)
  11. Convert decimal 49 to XS3 and to Gray. (Apr 2008)
  12. State DeMorgan’s  Theorems. (Apr 2008)
  13. Convert 1110011 into hexadecimal through octal. (Nov 2008)
  14. Prove that A + ‘ B – A + B, using Boolean algebra. (Nov 2008)
  15. State Consensus theorem. (Nov 2008)
  16. Find the decimal equivalent of (367)8. (Nov 2008)
  1. Convert the following binary number to octal and hexadecimal 111101000.0111. (Apr 2009)
  1. What is Karnaugh map? (Apr 2009)
  2. Find the 10’s complement of (935)11. (Apr 2009)
  3. Express the following switching circuits in binary logic notation. (Apr 2009)

_______________________________________________________________________________

___________________ Unit II__________________________________________

  1. Give the characteristics of CMOS family. ( Nov 2006)
  2. Compare totem pole and open collector output of TTL family. ( Nov 2006)
  3. Explain why the temperature sensitivity of HTL is significantly better than that of DTL.
  4. What are tri-state gates? ( Apr 2007)                                                          ( Apr 2007)
  5. Write down Fan in and Fan out of a standard TL IC. ( Nov 2007)
  6. Draw the tristate inverter and draw its truth table. ( Nov 2007)
  7. List the merits of TTL logic.  ( Nov 2007)
  8. What is meant by wired logic? ( Nov 2007)
  9. Give two advantages and one disadvantages of the totem pole arrangement. (Apr 2008)
  10. What is a tri-state gate? (Apr 2008)
  11. Compare two main features of TTL and CMOS logic gates. (Apr 2008)
  12. What are tri-state gates? (Apr 2008)
  13. Write down fan in and fan out of a standard TTL IC. (Nov 2008)
  14. Realize f = A’B + AB’ using minimum universal gates. (Nov 2008)
  15. Define Propagation delay. (Nov 2008)
  16. What are tri-state gates? (Nov 2008)
  17. List five series of TTL circuits (Apr 2009)
  18. In what type of application should ECL not be used? (Apr 2009)
  19. What do you mean by universal gate? (Apr 2009)
  20. Obtain the truth table of the function F = xy + x’y’ + y’z (Apr 2009)

______________________________________________________________________________

`Unit III

  1. Implement f = abcd using two input NAND Gate. ( Nov 2006)
  2. What is the difference between decoder and multiplexer? ( Nov 2006).
  3. Represent a half adder in block diagram form and also its logic implementation. ( Nov 2007)
  4. Differentiate Combinational circuit and Sequential circuit. ( Nov 2007)
  5. Minimize the four variable logic function using k-map. ( Apr 2007)
    f(A,B,C,D) =     Sm (0,1,2,3,5,7,8,9,11,14)
  6. Draw a full adder circuit. ( Apr 2007)
  7. Draw the diagram of Binary to Gray code converter? ( Nov 2007)
  8. How a demultiplier can be converted into a decoder? ( Nov 2007)
  9. Compare Encoder and decoder. (Apr 2008)
  10. What is meant by a magnitude comparator? (Apr 2008)
  11. Mention the types of adders. (Apr 2008)
  12. Which gate is suitable for building a comparator and why? (Apr 2008)
  13. Represent a Half adder in block diagram form and also its logic implementation. (Nov 2008)
  14. Define Priority Encoder. (Nov 2008)
  15. Draw Adder/Subtractor circuit. (Nov 2008)
  16. What is a decoder? (Nov 2008)
  17. Define the term glitch. (Apr 2009)
  18. Define the term strobing. (Apr 2009)
  19. What is state table? (Apr 2009)
  20. Draw the logic diagram of a master slave D-flip-flop using  NAND gate. (Apr 2009)

________________________________________________________________________________

Unit IV _____________________________________________________________________

  1. Define race around condition and explain how it can be eliminated. ( Nov 2006)
  2. Define lockout condition. ( Nov 2006)
  3. What is the drawback of SR Flipflop?  How is it minimized? ( Nov 2007)
  4. Draw a 2 bit Ripple Counter and convert this into a 2 bit Ring counter. ( Nov 2007)
  5. Write the excitation table of JK Flip Flop. ( Nov 2007)
  6. What are the different types of shift registers? ( Nov 2007)
  7. Write down the design steps of synchronous counters. ( Apr 2007)
  8. How do you carryout state minimization? ( Apr 2007)
  9. Draw the logic diagram of a master – slave D-flip flop using NAND gate. (Apr 2008)
  10. What do you mean by critical and Non-critical races? How can they be avoided? (Apr 2008)
  11. Build a D flip-flop from SR flip-flop IC. (Apr 2008)
  12. How are clocked sequential circuits used?  Give an example. (Apr 2008)
  13. What is the drawback of SR FF? How is this minimized? (Nov 2008)
  14. Define Synchronous counter. (Nov 2008)
  15. State a limitation of SR flipflop. (Nov 2008)
  16. If a serial-in-serial-out shift register has N stages and if the clock frequency is f, what will be the time delay between input and output? (Nov 2008)
  17. What do you mean by zero suppression? (Apr 2009)
  18. What is a carry? (Apr 2009)
  19. What is the difference between serial and parallel transfer? (Apr 2009)

20. What is edge triggered flip-flop? (Apr 2009)

_________________________________________________________________________________

UNIT V

  1. What are the types of asynchronous circuit? ( Nov 2006)
  2. Define essential hazard. ( Nov 2006)
  3. Explain race around condition. ( Apr 2007)
  4. What are essential hazards? ( Apr 2007)
  5. Define Race and Cycle. ( Nov 2007)
  6. Define Stable state. ( Nov 2007)
  7. What is a race condition? ( Nov 2007)
  8. What is Hazard? ( Nov 2007)
  9. Why are shift registers considered to be basic memory devices? (Apr 2008)
  10. How can essential hazards be eliminated? (Apr 2008)
  11. What are pulse mode sequential circuits? (Apr 2008)
  12. Define the racing condition. (Apr 2008)
  13. What is race? (Nov 2008)
  14. Define equivalence of two states in Asynchronous sequential circuits. (Nov 2008)
  15. What is a fundamental mode sequential circuit?
  16. What is the cause for essential hazard?
  17. What is the race condition? (Apr 2009)
  18. Give an example for sequential circuit. (Apr 2009)
  19. What is stable and unstable state? (Apr 2009)
  20. What do you mean by races? (Apr 2009)