digital logic theory(part B) questions……



Digital Logic Theory & Design

PART – B

Unit I

1. (a)For the logic expression, y = AB + ĀB, obtain the truth table.  ( Apr 2007)

(b)Make a K map for the function f = AB + AC’ + C + AD + ABC + AB’C.
Express f in standard SOP form. Minimize it and realize the minimized expression using NAND gates. ( Apr 2007)

2.Minimize the following expression using K-map and realise with NAND gates.
f₂ (A,B,C,D,E)            = PM (6,9,11,13,14,17,20,25,28,29,30) ( Apr 2007)

3.Find the reduced / minimal SOP representation for

f(A, B, C, D, E) = Σm(1, 4, 6, 10, 20, 22, 24, 26)+d(0, 11, 16, 27)

Using Karnaugh’s map method. ( Nov 2006)

4.Reduce by Tabulation method:        ( Nov 2006)

f(A, B, C, D, E) = Σm(1, 4, 8, 10, 11, 20, 22, 24)+d(0, 12, 16, 17)

1. (a)Reduce the following function using K Map

f = ABC’ + A’B’C + ABC + AB’C and realize using NAND gates only. ( Nov 2007) (8)

(b)Convert the following hexadecimal to decimal.

(i) 1C₁₆ (ii) A85₁₆ (iii) E5₁₆ (iv) B2F8₁₆ ( Nov 2007) (4)

1. Simplify using tabulation method.

F(w,x,y,z) = ∑(1,4,6,7,8,9,10,11,15). ( Nov 2007)

1. (a)Add 54 + (-78) using two’s complement arithmetic. ( Nov 2007)

(b)Minimize the following expression using Boolean Laws.

A’BC + A’B + A’B’C + ABC + ABC’ + AC’   ( Nov 2007)

1. Solve using K map and implement using basic gates.

F(A,B,C,D) = S m (1,2,3,4,5,9,10,12,13) ( Nov 2007)

1. Using the K-map method, Simplify the following functions into minimal sum of products

F(u,w,x,y,z)= ∑(0.2,5,7,9,11,13,15,16,18,21,23,25,27,29,31) ( May 2008)

1. Find the minimal sum of products for the Boolean expression,

F(a,b,c,d) = ∑(1,2,3,7,8,9,10,11,14,15) ( May 2008)

1. Determine the minimum expression for the following function     F = S m (0,2,3,4,6,7,8,12,14,15,16,18,19,20,22,23,24,28) using any one standard method.  Verify the result using tabular method. ( Apr 2008)

1. (a)Simplify the Boolean expression – F = (((A’B’C)’ _ A B)’ (CB’))’ and implement the same using Basic gates only, and then using NAND gates only Compare them.                                                  (8)

(b)   Obtain the standard SOP and POS forms of F = A + BC’. (4) ( Apr 2008)

1. Reduce the following function using K map F= ABC’+ A’B’C + ABC + AB’ C and realize using NAND gates only. ( Nov 2008)

1. List out any four basic rules that are used in Boolean algebra expressions and also explain the basic laws of Boolean algebra with sample. ( Nov 2008)

1. Simplify the Boolean function. F(A,B,C,D) = Sm(0,2,4,5,6,7,8,10,13,15) ( Nov 2008)

1. (a)  State and prove Demorgan’s law.

(b) Obtain the canonical sum of product form of the function Y(A,B,C) = A + BC. ( Nov 2008)

1. Perform the following conversions:

(a)435₁₀ to octal

(b)540₈ to binary

(c) 412₁₆ to binary

Also perform binary multiplication of

(i)     1001 x 110

(ii)   111 x 101     ( Apr 2009)

1. Design a digital system that adds and subtracts two binary fixed point numbers in sign 2’s complement form. ( Apr 2009)

1. Express the Boolean function F = x y + x’z in a product of maxterm form. ( Apr 2009)

1. Simplify the Boolean function

F(w x y z) =  by Karnaugh map technique. ( Apr 2009)

Unit II

1. List the performance characteristics of digital Ics and explain in detail. ( Apr 2007)

2.What are the disadvantages of DTL, Explain the operation of TTL with neat sketch. ( Apr 2007)

3.Draw the circuit diagram and explain the operation of two TTL NAND Gate with open collector output.                            ( Nov 2006)

4.With a neat diagram, explain the operation of two input CMOS NOR gate. ( Nov 2006)

1. Explain the working of HTL gate and obtain its noise margin value. ( Nov 2007)

1. (a) Explain the working of TTL tristate logic.                                    (8)

(b) Write about WIRED – AND logic.          ( Nov 2007) (4)

1. (a) Explain in detail about ECL logic for AND gate.             (7)

(b) Compare the RTL, DTL, TTL and ECL logic families.(5)  ( Nov 2007)

1. With neat diagram, explain the working of CMOS NAND gate. ( Nov 2007)

1. Discuss about the various parameters of TTL. ( May 2008)

1. (a) Draw the basic BICMOS inverter, NAND and NOR gates and explain its operation.

(b)   Draw and explain the circuit diagram of a 3-input I²L NOR gate. ( May 2008)

1. Discuss in brief about the digital logic families. ( Apr 2008)

1. Write short notes on:

(a) Wired- logic gates.                                                                                     (4)

(b) Characteristics of TTL and CMOS logic gates.                (8) ( Apr 2008)

1. Explain the working of HTL Gate and obtain its noise margin value. ( Nov 2008)

1. (a) Implement the expressions

(i)AB + BCD + EFGH

(ii) (A + B) (C+D+E) (F+G+H+I) with logic gates

(b)Implement the following function using a quad 2-input NOR gates.

F = (A’B+C).D’ ( Nov 2008)

1. Explain the working of two input TTL NAND gate. ( Nov 2008)

1. Explain the working of ECL NOR gate. ( Nov 2008)

1. (a) Describe the major difference between a bipolar integrated circuit and an MOS integrated circuit.                                                       (7)

(b) What are the advantages of ECL over other IC      technologies?  (5) ( Apr 2009)

1. (a)Does CMOS or TTL perform better in a high-noise environment? Why?   (7)

(b) Explain why an open TTL input acts as a HIGH.             (5) ( Apr 2009)

1. Implement the following function with either NAND or NOR gate. Use only four gates.  Only the normal Inputs are available.

1. F = w ‘x z + w’ y z + x’ y z’ + w x y’ z
2. D = w y z     ( Apr 2009)

1. An IC logic family has NAND gates with fan out of 5 and buffer gates with fan out of 10. Show how the output signal of a single NAND gate can be applied to 50 other gate inputs. ( Apr 2009)

Unit III

1. Draw the truth table of a full adder. Obtain the K – maps & realise the map using NAND – NAND gates. ( Apr 2007)
2. Design a parity generator circuit to add an even parity bit to a 14 bit word. Use two 74180 packages. ( Apr 2007)
   3.Design a binary to gray code converter. ( Nov 2006)

4.(a)What is a decoder?  Give the truth table of 3:8 decoder and supplement it using basic gate.  .(Nov 2006)

(b) Design a 4:1 Mux   . ( Nov 2006)

1. Realize            F(w,x,y,z) = ∑(1,4,6,7,8,9,10,11,15). Using 4 – to – 1 MUX. ( Nov 2007)

1. What is PAL? Show how PAL is programmed for following logic function.

X = AB’C + A’BC’ + A’B + AC. ( Nov 2007)

1. (a) Design a 3 x 8 decoder using basic gates.

(b) Design and explain a full adder circuit using 2 half adders. ( Nov 2007)

1. Implement 8 x 1 Multiplier for the given Boolean function.  Consider A,B,C as select lines and D as data input.

F(A,B,C,D) = Sm(0,1,2,4,7,8,12,13,15)  ( Nov 2007)

1. Explain briefly about the BCD – Seven Segment decoder. ( May 2008)

1. Draw and explain the basic block diagram of PLA and what are the steps used for implementing combinational circuit using PLA. ( May 2008)

1. What are Programmable Logic Devices? Write a descriptive note about them. ( Apr 2008)

1. Design a Binary to BCD code converter. ( Apr 2008)

1. Obtain the PLA program table with only seven product terms for a BCD to Excess 3 code converter.  Also give the fuse map. ( Nov 2008)

1. 1. Realize S(x,y,z) = S(1,2,4,5) using an appropriate decoder and an external logic gate.
   2. Construct a 5 x 32 decoder with four 3 x 5 decoders and a 2×4 decoder use block diagrams. ( Nov 2008)

1. Design a full adder and a comparator. ( Nov 2008)

1. 1. Explain the working of 8 to 1 multiplexer.
   2. Implement the function
2. F(A,B,C) = Sm(1,3,5,6)using 8 to 1 multiplexer. ( Nov 2008)

1. Implements a full adder circuit with a decoder and two OR gates.                                                                                                                           (8)
2. (b) Explain how a PLA differs from a ROM.                                    (4) ( Apr 2009)

1. Explain the working of following circuits:
   1. MUX
   2. DEMUX
   3. Encoder/ Decoder. ( Apr 2009)

1. Show how full adder circuits can be converted into full subtractor with the addition of one inverter circuits. ( Apr 2009)

1. Design a combinational circuit that accepts a three bit number and generate an output binary number equal to the square of the input number. ( Apr 2009)

Unit IV

1. Explain the operation of ring counter and give its state diagram. ( Apr 2007)

2.Design a clocked sequential circuit for the state diagram shown below. ( Apr 2007)

Diagram

3. Design a sequential circuit for the given state diagram.  . ( Nov 2006)

diagram

4.Design a synchronous counter for

(a)    4 → 6 → 7 → 3 → 1 → 4 . . .

Avoid lock out condition.  Use JK type design.  . ( Nov 2006)

1. Design and implement a binary to Gray code Converter. ( Nov 2007)

1. (a)Draw the logic diagram for a master slave JK flipflop and explain.

(b) Draw four bit serial in serial out shift register and explain. ( Nov 2007)

1. Consider the following state diagram.

Write down the state table and derive the minimized Boolean expression for implementing the next state and output functions.  Use T type flip – flop. ( Nov 2007)

1. Design a synchronous counter that counts the sequence 0,1,2,6,3,1,0… using D flip – flop.

( Nov 2007)

1. Design a synchronous counter with the following sequence counter

0000         0100        0100       0110       1000      1010       1100       1110          0000.  ( May 2008)

1. (a)Explain the working of serial in parallel out shift register with logic diagram and waveforms.

(b)Explain about the various applications of flip-flops. ( May 2008)

1. With a neat sketch of the circuit describe a JK Master-Slave Flip-flop. ( Apr 2008)

1. Design a mod – 3 synchronous counter. ( Apr 2008)

1. (a)Draw a Four bit serial in serial out shift register and explain.

(b)Draw the Eight bit serial in parallel out Shift register and explain its operation. ( Nov 2008)

1. (a) Draw the logic diagram for a master slave JK FF and      explain.                                                                                                                                    (8)

(b) Draw the 4 bit Johnson counter.                                      (4) ( Nov 2008)

1. Explain the working of master-slave JK flipflop. ( Nov 2008)

1. Design and explain the working of 4 bit up-down counter. ( Nov 2008)

1. Design a counter using T flip-flop for binary counting sequence: 0, 1, 3, 7, 6, 4 and repeat. ( Apr 2009)

1. Design BCD to decimal decoder. ( Apr 2009)

1. Design a counter that counts that decimal digits according to the 2,4,2 use T- flip-flop. ( Apr 2009)

1. A sequential circuits has two flip-flop (A and B), two input (x and y), and an output (z).  The flip-flop input function and output function are as follows.

JA = X a = y’B’                                        KA = x y’ B’

JB = x A’                                                              KB = X y’ + B

Z = x y A + x’ y’ B

Obtain logic diagram, state table, state diagram and state equation. ( Apr 2009)

Unit V

1. Compare the performance of synchronous circuits with asynchronous circuits in relation to (i)       Races (ii)            Hazards. ( Apr 2007)
2. Write short notes on Pulse mode sequential circuits. ( Apr 2007)

3.Design a gated latch with two inputs G(gate) D(data) and one output Q. . ( Nov 2006)

4.Write notes on Asynchronous and synchronous sequential circuits design. . ( Nov 2006)

1. (a) Reduce the state table using implication chart method.    (8) ( Nov 2007)

Present State	a	b	c	d	e	f	g
Next State X = 0	a	c	a	e	a	g	a
Next State X = 1	b	d	d	f	f	f	f
Output	0	0	0	1	1	1	1

(b) Write about race free assignment.                   ( Nov 2007) (4)

1. (a) Explain principle of pulse mode asynchronous sequential logic circuit.  What are the restrictions to be lain on the input signal of a pulse mode asynchronous sequential circuit?            (8)

(b) What is an Essential Hazard?  Why does it occur?  Suggest methods to have essential hazard free circuit.                  ( Nov 2007) (4)

1. Write short notes on Stable and unstable states. ( Nov 2007)
2. Discuss on essential hazards and pulse mode sequential circuits. ( Nov 2007)

1. Obtain a static hazard free asynchronous circuit for the following switching function.

i. F = ∑(0,2,4,5,8,10,14) ( May 2008)

1. Design an asynchronous circuit that will output  only the first pulse received whatever a control input is asserted from LOW to HIGH state. Any future pulses will be ignored. ( May 2008)

(ii) Timing Diagram

1. Make short descriptions on:

(a) States and output specifications.                                                         (4)

(b) Race free assignments.                                                                        (8)        ( Apr 2008)

1. What are Hazards in sequential circuits?  State their effects and also types.  Discuss the salient features in detail. ( Apr 2008)

1. Define Sequential circuit and illustrate mixed operating mode sequential circuit model. ( Nov 2008)

1. Define the following terms.

(a)    Critical race

(b)   Non Critical race

(c)    Hazard

(d)   Flow table

(e)    Static and Dynamic essential hazards.

( Nov 2008)

1. Write note on cycles and races. ( Nov 2008)

1. (a)What are hazards?

(b)Obtain an hazard free circuit for the Boolean function F(A,B,C,D) = S m (1,3,6,7,13,15)

( Nov 2008)

1. (a)Write down the output specifications of sequential circuit.(8)

(b) Describe about stable and unstable states of sequential     circuit.                                                                                                                              (4) ( Apr 2009)

1. Write short notes on:

(a)    Application of sequential circuits

(b)   Race free assignment.

(c)    Hazards. ( Apr 2009)

1. Write short notes on:   (a) Hazards      (b) Race free assignment. ( Apr 2009)
2. Explain the pulse made sequential circuit in detail. ( Apr 2009)

digital logic theory(part A) questions…….

Digital Logic Theory & Design

PART – A

Date: 17-11-2006 Unit I

1. Convert (673.124)₈ into binary numbers.( Nov 2006)
2. State deMorgan’s law. ( Nov 2006)
3. Given the logic expression f = ABC + BC’D + ĀBC, make a truth table.( Apr 2007)
4. State the Boolean theorems. ( Apr 2007)
5. Convert 1110011 into hexadecimal through octal. ( Nov 2007)
6. Simplify A + AB + A’ + B ( Nov 2007)
7. Convert (110101)₂ to Octal number. ( Nov 2007)
8. Prove De Morgan’s theorem. ( Nov 2007)
9. Express the following decimal numbers in 2421 and 5421 code (i) 1993 (Apr 2008)
10. State Demorgan’s theorem. (Apr 2008)
11. Convert decimal 49 to XS3 and to Gray. (Apr 2008)
12. State DeMorgan’s  Theorems. (Apr 2008)
13. Convert 1110011 into hexadecimal through octal. (Nov 2008)
14. Prove that A + ‘ B – A + B, using Boolean algebra. (Nov 2008)
15. State Consensus theorem. (Nov 2008)
16. Find the decimal equivalent of (367)₈. (Nov 2008)

1. Convert the following binary number to octal and hexadecimal 111101000.0111. (Apr 2009)

1. What is Karnaugh map? (Apr 2009)
2. Find the 10’s complement of (935)₁₁. (Apr 2009)
3. Express the following switching circuits in binary logic notation. (Apr 2009)

_______________________________________________________________________________

___________________ Unit II__________________________________________

1. Give the characteristics of CMOS family. ( Nov 2006)
2. Compare totem pole and open collector output of TTL family. ( Nov 2006)
3. Explain why the temperature sensitivity of HTL is significantly better than that of DTL.
4. What are tri-state gates? ( Apr 2007)                                                          ( Apr 2007)
5. Write down Fan in and Fan out of a standard TL IC. ( Nov 2007)
6. Draw the tristate inverter and draw its truth table. ( Nov 2007)
7. List the merits of TTL logic.  ( Nov 2007)
8. What is meant by wired logic? ( Nov 2007)
9. Give two advantages and one disadvantages of the totem pole arrangement. (Apr 2008)
10. What is a tri-state gate? (Apr 2008)
11. Compare two main features of TTL and CMOS logic gates. (Apr 2008)
12. What are tri-state gates? (Apr 2008)
13. Write down fan in and fan out of a standard TTL IC. (Nov 2008)
14. Realize f = A’B + AB’ using minimum universal gates. (Nov 2008)
15. Define Propagation delay. (Nov 2008)
16. What are tri-state gates? (Nov 2008)
17. List five series of TTL circuits (Apr 2009)
18. In what type of application should ECL not be used? (Apr 2009)
19. What do you mean by universal gate? (Apr 2009)
20. Obtain the truth table of the function F = xy + x’y’ + y’z (Apr 2009)

______________________________________________________________________________

`Unit III

1. Implement f = abcd using two input NAND Gate. ( Nov 2006)
2. What is the difference between decoder and multiplexer? ( Nov 2006).
3. Represent a half adder in block diagram form and also its logic implementation. ( Nov 2007)
4. Differentiate Combinational circuit and Sequential circuit. ( Nov 2007)
5. Minimize the four variable logic function using k-map. ( Apr 2007)
   f(A,B,C,D) = Sm (0,1,2,3,5,7,8,9,11,14)
6. Draw a full adder circuit. ( Apr 2007)
7. Draw the diagram of Binary to Gray code converter? ( Nov 2007)
8. How a demultiplier can be converted into a decoder? ( Nov 2007)
9. Compare Encoder and decoder. (Apr 2008)
10. What is meant by a magnitude comparator? (Apr 2008)
11. Mention the types of adders. (Apr 2008)
12. Which gate is suitable for building a comparator and why? (Apr 2008)
13. Represent a Half adder in block diagram form and also its logic implementation. (Nov 2008)
14. Define Priority Encoder. (Nov 2008)
15. Draw Adder/Subtractor circuit. (Nov 2008)
16. What is a decoder? (Nov 2008)
17. Define the term glitch. (Apr 2009)
18. Define the term strobing. (Apr 2009)
19. What is state table? (Apr 2009)
20. Draw the logic diagram of a master slave D-flip-flop using  NAND gate. (Apr 2009)

________________________________________________________________________________

Unit IV _____________________________________________________________________

1. Define race around condition and explain how it can be eliminated. ( Nov 2006)
2. Define lockout condition. ( Nov 2006)
3. What is the drawback of SR Flipflop?  How is it minimized? ( Nov 2007)
4. Draw a 2 bit Ripple Counter and convert this into a 2 bit Ring counter. ( Nov 2007)
5. Write the excitation table of JK Flip Flop. ( Nov 2007)
6. What are the different types of shift registers? ( Nov 2007)
7. Write down the design steps of synchronous counters. ( Apr 2007)
8. How do you carryout state minimization? ( Apr 2007)
9. Draw the logic diagram of a master – slave D-flip flop using NAND gate. (Apr 2008)
10. What do you mean by critical and Non-critical races? How can they be avoided? (Apr 2008)
11. Build a D flip-flop from SR flip-flop IC. (Apr 2008)
12. How are clocked sequential circuits used?  Give an example. (Apr 2008)
13. What is the drawback of SR FF? How is this minimized? (Nov 2008)
14. Define Synchronous counter. (Nov 2008)
15. State a limitation of SR flipflop. (Nov 2008)
16. If a serial-in-serial-out shift register has N stages and if the clock frequency is f, what will be the time delay between input and output? (Nov 2008)
17. What do you mean by zero suppression? (Apr 2009)
18. What is a carry? (Apr 2009)
19. What is the difference between serial and parallel transfer? (Apr 2009)

20. What is edge triggered flip-flop? (Apr 2009)

_________________________________________________________________________________

UNIT V

1. What are the types of asynchronous circuit? ( Nov 2006)
2. Define essential hazard. ( Nov 2006)
3. Explain race around condition. ( Apr 2007)
4. What are essential hazards? ( Apr 2007)
5. Define Race and Cycle. ( Nov 2007)
6. Define Stable state. ( Nov 2007)
7. What is a race condition? ( Nov 2007)
8. What is Hazard? ( Nov 2007)
9. Why are shift registers considered to be basic memory devices? (Apr 2008)
10. How can essential hazards be eliminated? (Apr 2008)
11. What are pulse mode sequential circuits? (Apr 2008)
12. Define the racing condition. (Apr 2008)
13. What is race? (Nov 2008)
14. Define equivalence of two states in Asynchronous sequential circuits. (Nov 2008)
15. What is a fundamental mode sequential circuit?
16. What is the cause for essential hazard?
17. What is the race condition? (Apr 2009)
18. Give an example for sequential circuit. (Apr 2009)
19. What is stable and unstable state? (Apr 2009)
20. What do you mean by races? (Apr 2009)

previous question papers……(thermal engg 4th sem)

SATHYABAMA UNIVERSITY

(Established under section 3 of UGC Act, 1956)

Course & Branch: B.E – E&C/EIE

Title of the paper: Thermal Engineering

Semester: IV                                                                   Max.Marks: 80

Sub.Code: 418403-517403-518403-6C0048(2006-2007)      Time: 3 Hours

Date: 29-04-2009                                                            Session: FN

PART – A     (10 x 2 = 20)

Answer All the Questions

1.     What are the limitations of first law of thermodynamics?

2.     State clausius statement.

3.     Define dryness fraction.

4.     What are the functions of condensers?

5.     What are the assumptions made for deriving efficiency of air         standard cycles?

6.     Differentiate IHP and BHP.

7.     Define the term free air delivery.

8.     What are the uses of multistage compression?

9.     What are the modes of heat transfer? Explain?

10.   Define relative humidity.

PART – B    (5 x 12 = 60)

Answer All the Questions

11.   (a) Derive an expression for work done for an adiabatic non flow  process.  (4)

(b) The initial volume of 0.18 kg of a certain gas was 0.15m³ at a         temperature of 15°C and a pressure of 1 bar.  After adiabatic         compression to 0.056m³ the pressure was found to be 4 bar.  Find gas constant, molecular mass of  the gas, ratio of specific heats, two specific heats and change of internal energy.   (8)

(or)

12.   (a) Derive steady flow energy equations.     (4)

(b) The velocity and enthalpy of fluid at the inlet of a certain     nozzle are 50m/s and 2800 kJ/kg. The enthalpy at the exit of nozzle is 2600 kJ/kg.  The nozzle is horizontal and insulated so      that no heat transfer takes place from it.  Find velocity of fluid at   exit.

Mass flow rate, Area at inlet is 0.09m²

Specific volume is 0.185m³/kg

Exit area of the nozzle, specific volume

at exit is 0.495m³/kg   (8)

13.   (a) Determine the volume of 1kg of superheated steam at a  pressure of 20 bar and temperature of 300°C. (4)

(b) A vessel contains 2kg of steam of a  pressure of 8 bar.  Find the amount of heat which must be rejected so as to reduce the quality     of steam to be 70%. (8)

(or)

14.   (a) A steam turbine receives steam at 15 bar and 350°C and  exhausts to the condenser at 0.06bar.  Determine the thermal         efficiency of the Rankine cycle.   (4)

(b) Explain with neat sketch any one type of cooling tower.        (8)

15.   Derive air standard efficiency of Diesel cycle.                     (12)

(or)

16.   A petrol engine gave the following results when loaded with      friction brake during a test of an hour’s duration.

Cylinder diameter 240mm, stroke length: 480mm, clearance volume: 4450×10^-6m³, circumference of the brake wheel: 3.      net load on brake 1260N at 226.7rpm average explosion/min: 77, m.e.p: 7.5 bar. Gas useed 13 m³/h at 15°C and 771mm of Hg, LCV: 49350 kJ/m³, Cooling water 660kg raised to 34.2° heat lost to exhaust gas 8% calculate: IHP, BHP, òIndicated, òratio and also draw a heat balance sheet.

17.   Derive an expression for minimum work required for a 2 stage  reciprocating air compressor.   (12)

(or)

18.   (a) A multistage air compressor is to be designed to elevate the  pressure from 1 bar to 100 bar such that the stage pressure ratio will not exceed 4. Determine no. of stages, exact stage pressure  ratio intermediate pressure. (6)

(b) With neat sketches explain (i) vahe  type and

(ii) 100h blower  (6)

19.   Derive three dimensional Fourier conduction equation.       (12)

(or)

20.   (a) Explain with a neat sketch the mechanism of a simple vapour compression Refrigeration system.   (8)

(b) What are the advantages of vapour Absorption over vapour Compression Refrigeration Systems?     (4)

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